APA (7th ed.) Citation

PRASAD, T. J., CHENNAKESAVULU, M., REDDY, B. A. R., RAO, V. S., & HUSSAIN, S. K. (2025). Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process. Journal of Active & Passive Electronic Devices, 19(4), 283.

Chicago Style (17th ed.) Citation

PRASAD, T. JAYACHANDRA, M. CHENNAKESAVULU, BOJJ A. RAMESH REDDY, VADDE SEETHARAMA RAO, and SHAIK KASHIF HUSSAIN. "Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process." Journal of Active & Passive Electronic Devices 19, no. 4 (2025): 283.

MLA (9th ed.) Citation

PRASAD, T. JAYACHANDRA, et al. "Optimized High Speed Design of Arithmetic BCD Block Utilizing Complementary MOS Process." Journal of Active & Passive Electronic Devices, vol. 19, no. 4, 2025, p. 283.