A 48.1 ps HEMT DCFL NAND circuit with a dual gate structure.
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| Title: | A 48.1 ps HEMT DCFL NAND circuit with a dual gate structure. |
|---|---|
| Authors: | Suehiro, H., Miyata, T., Hara, N. |
| Source: | Solid-State Electronics; September 1995, Vol. 38, p1717-1721, 5p |
| Database: | Applied Science & Technology Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: aci DbLabel: Applied Science & Technology Source An: 500320073 AccessLevel: 2 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: A 48.1 ps HEMT DCFL NAND circuit with a dual gate structure. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AU" term="%22Suehiro%2C+H%2E%22">Suehiro, H.</searchLink><br /><searchLink fieldCode="AU" term="%22Miyata%2C+T%2E%22">Miyata, T.</searchLink><br /><searchLink fieldCode="AU" term="%22Hara%2C+N%2E%22">Hara, N.</searchLink> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Solid-State+Electronics%22">Solid-State Electronics</searchLink>; September 1995, Vol. 38, p1717-1721, 5p |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=aci&AN=500320073 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/0038-1101(95)00040-Z Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 5 StartPage: 1717 Titles: – TitleFull: A 48.1 ps HEMT DCFL NAND circuit with a dual gate structure. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Suehiro, H. – PersonEntity: Name: NameFull: Miyata, T. – PersonEntity: Name: NameFull: Hara, N. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: September 1995 Type: published Y: 1995 Identifiers: – Type: issn-print Value: 00381101 Numbering: – Type: volume Value: 38 Titles: – TitleFull: Solid-State Electronics Type: main |
| ResultId | 1 |
