APA (7th ed.) Citation

Shieh, M., Wang, T., & Yang, D. (2009). Low-power register-exchange survivor memory architectures for Viterbi decoders. IET Circuits, Devices & Systems, 3(2), 83. https://doi.org/10.1049/iet-cds.2008.0262

Chicago Style (17th ed.) Citation

Shieh, M.-D, T.-P Wang, and D.-W Yang. "Low-power Register-exchange Survivor Memory Architectures for Viterbi Decoders." IET Circuits, Devices & Systems 3, no. 2 (2009): 83. https://doi.org/10.1049/iet-cds.2008.0262.

MLA (9th ed.) Citation

Shieh, M.-D, et al. "Low-power Register-exchange Survivor Memory Architectures for Viterbi Decoders." IET Circuits, Devices & Systems, vol. 3, no. 2, 2009, p. 83, https://doi.org/10.1049/iet-cds.2008.0262.