Low-power register-exchange survivor memory architectures for Viterbi decoders.
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| Title: | Low-power register-exchange survivor memory architectures for Viterbi decoders. |
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| Authors: | Shieh, M.-D., Wang, T.-P., Yang, D.-W. |
| Source: | IET Circuits, Devices & Systems; April 2009, Vol. 3 Issue 2, p83-90, 8p |
| Database: | Applied Science & Technology Source |
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