Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements.
Saved in:
| Title: | Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements. |
|---|---|
| Authors: | Iwata, Hiroshi1 (AUTHOR) iwata@info.nara-k.ac.jp, Yamasaki, Kokoro1 (AUTHOR), Yamaguchi, Ken'ichi1 (AUTHOR) |
| Source: | Journal of Electronic Testing. Aug2024, Vol. 40 Issue 4, p497-508. 12p. |
| Database: | Academic Search Ultimate |
| ISSN: | 09238174 |
|---|---|
| DOI: | 10.1007/s10836-024-06128-4 |
