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Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements.

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Bibliographic Details
Title: Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements.
Authors: Iwata, Hiroshi1 (AUTHOR) iwata@info.nara-k.ac.jp, Yamasaki, Kokoro1 (AUTHOR), Yamaguchi, Ken'ichi1 (AUTHOR)
Source: Journal of Electronic Testing. Aug2024, Vol. 40 Issue 4, p497-508. 12p.
Database: Academic Search Ultimate
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