Evaluation of design and verification techniques for synthesizable low power 8-Bit RISC microprocessors.
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| Title: | Evaluation of design and verification techniques for synthesizable low power 8-Bit RISC microprocessors. |
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| Authors: | Ujwal, B. S.1 (AUTHOR) ujwalshankar7@gmail.com, Sanjana, H. S.1 (AUTHOR) sanjanasatisha@gmail.com, Thanishka, K.1 (AUTHOR) thanishkakreddy@gmail.com, Shirur, Yasha Jyothi M.1 (AUTHOR) yashajyothimshirur@bnmit.in, Munavalli, Jyoti R.1 (AUTHOR) jyotirmunavalli@bnmit.in |
| Source: | AIP Conference Proceedings. 2026, Vol. 3426 Issue 1, p1-8. 8p. |
| Database: | Academic Search Ultimate |
| ISSN: | 0094243X |
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| DOI: | 10.1063/5.0327664 |
