An Area Efficient Approach to Realize Vedic Multiplier using 4–2 Compressor adder for Image processing Applications.
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| Title: | An Area Efficient Approach to Realize Vedic Multiplier using 4–2 Compressor adder for Image processing Applications. |
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| Authors: | Dhanasekar, S.1 (AUTHOR) dhanasekar.sm@gmail.com, Govindaraj, V.2 (AUTHOR), Augustine Fletcher, A. S.3 (AUTHOR) |
| Source: | International Journal of Electronics. May2026, Vol. 113 Issue 5, p937-957. 21p. |
| Database: | Business Source Ultimate |
| ISSN: | 00207217 |
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| DOI: | 10.1080/00207217.2025.2565740 |
