APA (7th ed.) Citation

Dhanasekar, S., Govindaraj, V., & Augustine Fletcher, A. S. (2026). An Area Efficient Approach to Realize Vedic Multiplier using 4–2 Compressor adder for Image processing Applications. International Journal of Electronics, 113(5), 937. https://doi.org/10.1080/00207217.2025.2565740

Chicago Style (17th ed.) Citation

Dhanasekar, S., V. Govindaraj, and A. S. Augustine Fletcher. "An Area Efficient Approach to Realize Vedic Multiplier Using 4–2 Compressor Adder for Image Processing Applications." International Journal of Electronics 113, no. 5 (2026): 937. https://doi.org/10.1080/00207217.2025.2565740.

MLA (9th ed.) Citation

Dhanasekar, S., et al. "An Area Efficient Approach to Realize Vedic Multiplier Using 4–2 Compressor Adder for Image Processing Applications." International Journal of Electronics, vol. 113, no. 5, 2026, p. 937, https://doi.org/10.1080/00207217.2025.2565740.