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An Area Efficient Approach to Realize Vedic Multiplier using 4–2 Compressor adder for Image processing Applications.

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Title: An Area Efficient Approach to Realize Vedic Multiplier using 4–2 Compressor adder for Image processing Applications.
Authors: Dhanasekar, S.1 (AUTHOR) dhanasekar.sm@gmail.com, Govindaraj, V.2 (AUTHOR), Augustine Fletcher, A. S.3 (AUTHOR)
Source: International Journal of Electronics. May2026, Vol. 113 Issue 5, p937-957. 21p.
Database: Business Source Ultimate
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Header DbId: bsu
DbLabel: Business Source Ultimate
An: 192698582
AccessLevel: 2
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: An Area Efficient Approach to Realize Vedic Multiplier using 4–2 Compressor adder for Image processing Applications.
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  Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Electronics%22">International Journal of Electronics</searchLink>. May2026, Vol. 113 Issue 5, p937-957. 21p.
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      – Type: doi
        Value: 10.1080/00207217.2025.2565740
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      – Code: eng
        Text: English
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        PageCount: 21
        StartPage: 937
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      – TitleFull: An Area Efficient Approach to Realize Vedic Multiplier using 4–2 Compressor adder for Image processing Applications.
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            NameFull: Dhanasekar, S.
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            NameFull: Govindaraj, V.
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              Text: May2026
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              Y: 2026
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              Value: 113
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