Bibliographic Details
| Title: |
Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. |
| Authors: |
Zhou, Yanhong1, Wang, Tiancheng1, Li, Huawei1, Lv, Tao1, Li, Xiaowei1 |
| Source: |
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Jun2016, Vol. 35 Issue 6, p999-1011. 13p. |
| Subjects: |
Integrated circuits, Test generators, Mathematical models, Data mining, Simulation methods & models |
| Abstract: |
Test generation for hard-to-reach states is important in functional verification. In this paper, we present a path constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for path constraint extraction and mutation, and uses a sequential path constraint extractor to generate a set of valid input vectors for exploring different simulation paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |