Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving.
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| Title: | Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. |
|---|---|
| Authors: | Zhou, Yanhong1, Wang, Tiancheng1, Li, Huawei1, Lv, Tao1, Li, Xiaowei1 |
| Source: | IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Jun2016, Vol. 35 Issue 6, p999-1011. 13p. |
| Subjects: | Integrated circuits, Test generators, Mathematical models, Data mining, Simulation methods & models |
| Abstract: | Test generation for hard-to-reach states is important in functional verification. In this paper, we present a path constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for path constraint extraction and mutation, and uses a sequential path constraint extractor to generate a set of valid input vectors for exploring different simulation paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 115559715 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Zhou%2C+Yanhong%22">Zhou, Yanhong</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Wang%2C+Tiancheng%22">Wang, Tiancheng</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Li%2C+Huawei%22">Li, Huawei</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Lv%2C+Tao%22">Lv, Tao</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Li%2C+Xiaowei%22">Li, Xiaowei</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Computer-Aided+Design+of+Integrated+Circuits+%26+Systems%22">IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems</searchLink>. Jun2016, Vol. 35 Issue 6, p999-1011. 13p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Test+generators%22">Test generators</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+models%22">Mathematical models</searchLink><br /><searchLink fieldCode="DE" term="%22Data+mining%22">Data mining</searchLink><br /><searchLink fieldCode="DE" term="%22Simulation+methods+%26+models%22">Simulation methods & models</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Test generation for hard-to-reach states is important in functional verification. In this paper, we present a path constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for path constraint extraction and mutation, and uses a sequential path constraint extractor to generate a set of valid input vectors for exploring different simulation paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TCAD.2015.2481863 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 999 Subjects: – SubjectFull: Integrated circuits Type: general – SubjectFull: Test generators Type: general – SubjectFull: Mathematical models Type: general – SubjectFull: Data mining Type: general – SubjectFull: Simulation methods & models Type: general Titles: – TitleFull: Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Zhou, Yanhong – PersonEntity: Name: NameFull: Wang, Tiancheng – PersonEntity: Name: NameFull: Li, Huawei – PersonEntity: Name: NameFull: Lv, Tao – PersonEntity: Name: NameFull: Li, Xiaowei IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 06 Text: Jun2016 Type: published Y: 2016 Identifiers: – Type: issn-print Value: 02780070 Numbering: – Type: volume Value: 35 – Type: issue Value: 6 Titles: – TitleFull: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems Type: main |
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