View in EDS

Exploring multiprocessor approaches to time series analysis.

Saved in:
Bibliographic Details
Title: Exploring multiprocessor approaches to time series analysis.
Authors: Quislant, Ricardo1 (AUTHOR) quislant@uma.es, Gutierrez, Eladio1 (AUTHOR) eladio@uma.es, Plata, Oscar1 (AUTHOR) oplata@uma.es
Source: Journal of Parallel & Distributed Computing. Jun2024, Vol. 188, pN.PAG-N.PAG. 1p.
Subjects: Intel Corp., Multiprocessors, Time series analysis, Environmental sciences
Abstract: Time series analysis is a key technique for extracting and predicting events in domains as diverse as epidemiology, genomics, neuroscience, environmental sciences, economics, etc. Matrix Profile , a state-of-the-art algorithm to perform time series analysis, finds out the most similar and dissimilar subsequences in a time series in deterministic time and it is exact. Matrix Profile has low arithmetic intensity and it operates on large amounts of time series data, which can be an issue in terms of memory requirements. On the other hand, Hardware Transactional Memory (HTM) is an alternative optimistic synchronization method that executes transactions speculatively in parallel while keeping track of memory accesses to detect and resolve conflicts. This work evaluates one of the best implementations of Matrix Profile exploring multiple multiprocessor variants and proposing new implementations that consider a variety of synchronization methods (HTM, locks, barriers), as well as algorithm organizations. We analyze these variants using real datasets, both short and large, in terms of speedup and memory requirements, the latter being a major issue when dealing with very large time series. The experimental evaluation shows that our proposals can achieve up to 100× speedup over the sequential algorithm for 128 threads, and up to 3× over the baseline, while keeping memory requirements low and even independent of the number of threads. • We explore multiprocessor approaches to Matrix Profile using locks, HTM, and tiling organizations. • We propose two HTM versions, one with tiling, yielding the best performance, and the other requiring the lowest memory footprint. • We propose a tiling approach using barriers with remarkable speedup and the lowest memory requirements. • We come up with a heuristic to choose the proper tile size and thread count depending on the time series parameters. • Our proposals show speedups between 2x and 3x over the baseline, and memory requirements independent of the number of threads. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Parallel & Distributed Computing is the property of Academic Press Inc. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
Description
Abstract:Time series analysis is a key technique for extracting and predicting events in domains as diverse as epidemiology, genomics, neuroscience, environmental sciences, economics, etc. Matrix Profile , a state-of-the-art algorithm to perform time series analysis, finds out the most similar and dissimilar subsequences in a time series in deterministic time and it is exact. Matrix Profile has low arithmetic intensity and it operates on large amounts of time series data, which can be an issue in terms of memory requirements. On the other hand, Hardware Transactional Memory (HTM) is an alternative optimistic synchronization method that executes transactions speculatively in parallel while keeping track of memory accesses to detect and resolve conflicts. This work evaluates one of the best implementations of Matrix Profile exploring multiple multiprocessor variants and proposing new implementations that consider a variety of synchronization methods (HTM, locks, barriers), as well as algorithm organizations. We analyze these variants using real datasets, both short and large, in terms of speedup and memory requirements, the latter being a major issue when dealing with very large time series. The experimental evaluation shows that our proposals can achieve up to 100× speedup over the sequential algorithm for 128 threads, and up to 3× over the baseline, while keeping memory requirements low and even independent of the number of threads. • We explore multiprocessor approaches to Matrix Profile using locks, HTM, and tiling organizations. • We propose two HTM versions, one with tiling, yielding the best performance, and the other requiring the lowest memory footprint. • We propose a tiling approach using barriers with remarkable speedup and the lowest memory requirements. • We come up with a heuristic to choose the proper tile size and thread count depending on the time series parameters. • Our proposals show speedups between 2x and 3x over the baseline, and memory requirements independent of the number of threads. [ABSTRACT FROM AUTHOR]
ISSN:07437315
DOI:10.1016/j.jpdc.2024.104855