Subgraph matching-based reference placement for printed circuit board designs.
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| Title: | Subgraph matching-based reference placement for printed circuit board designs. |
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| Authors: | Zhu, Ziran1 (AUTHOR) zrzhu@seu.edu.cn, Li, Yilin1 (AUTHOR), Su, Miaodi2 (AUTHOR), Zhang, Shu2 (AUTHOR), Su, Haiyuan2 (AUTHOR), Xiao, Yifeng3 (AUTHOR), He, Huan4 (AUTHOR), Chen, Jianli5 (AUTHOR), Chang, Yao-Wen6,7 (AUTHOR) |
| Source: | Journal of Supercomputing. Nov2024, Vol. 80 Issue 16, p24324-24357. 34p. |
| Subjects: | Data structures, Printed circuit design, Circuit complexity, Printed circuits, Isomorphism (Mathematics) |
| Abstract: | Reference placement is promising to handle the increasing complexity in printed circuit board (PCB) designs, which aims to find the isomorphism of the placed template in component combination to reuse the placement. In this paper, we convert the netlist information into a graph and then model the reference placement as a subgraph matching problem. Since the state-of-the-art subgraph matching methods usually recursively search the solutions and suffer from high time and memory consumption in large-scale designs, we develop a novel subgraph matching algorithm D2BS with diversity tolerance and improved backtracking to guarantee matching quality and efficiency. The D2BS algorithm is founded on a data structure called the candidate space (CS) structure. We build and filter the candidate set for each query node according to our designed features to construct the CS structure. During the CS optimization process, a graph diversity tolerance strategy is adopted to achieve efficient inexact matching. Then, hierarchical matching is developed to search the template embeddings in the CS structure guided by branch backtracking and matched-node snatching strategies. Based on the industrial PCB designs, experimental results show that D2BS outperforms the state-of-the-art subgraph matching method in matching accuracy and running time. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | Reference placement is promising to handle the increasing complexity in printed circuit board (PCB) designs, which aims to find the isomorphism of the placed template in component combination to reuse the placement. In this paper, we convert the netlist information into a graph and then model the reference placement as a subgraph matching problem. Since the state-of-the-art subgraph matching methods usually recursively search the solutions and suffer from high time and memory consumption in large-scale designs, we develop a novel subgraph matching algorithm D2BS with diversity tolerance and improved backtracking to guarantee matching quality and efficiency. The D2BS algorithm is founded on a data structure called the candidate space (CS) structure. We build and filter the candidate set for each query node according to our designed features to construct the CS structure. During the CS optimization process, a graph diversity tolerance strategy is adopted to achieve efficient inexact matching. Then, hierarchical matching is developed to search the template embeddings in the CS structure guided by branch backtracking and matched-node snatching strategies. Based on the industrial PCB designs, experimental results show that D2BS outperforms the state-of-the-art subgraph matching method in matching accuracy and running time. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 09208542 |
| DOI: | 10.1007/s11227-024-06338-9 |
