Inherent Fault-Tolerant Multilevel Inverter.
Saved in:
| Title: | Inherent Fault-Tolerant Multilevel Inverter. |
|---|---|
| Authors: | Phukan, Hillol1 (AUTHOR) hillol_rs@ee.nits.ac.in, Tiwari, Dinesh Kumar1 (AUTHOR) dinesh21_rs@ee.nits.ac.in, Singh, Jiwanjot2 (AUTHOR) jiwanjot@nith.ac.in, Pati, Avadh1 (AUTHOR) avadh@ee.nits.ac.in |
| Source: | Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Jul2025, Vol. 50 Issue 14, p10593-10609. 17p. |
| Subjects: | Power semiconductor switches, Pulse width modulation, Failed states, Topology |
| Abstract: | Due to the many semiconductor switches used in power conversion, switch failures are more common in multilevel inverters (MLIs). Therefore, designing an MLI with fault-tolerant (FT) capability is of utmost importance for uninterrupted supply. This article demonstrates various fault scenarios and offers numerous switching strategies for the different fault combinations. The detailed analysis of the proposed topology in terms of single (FT1), double (FT2), triple (FT3), quadruple (FT4), and quintuple (FT5) switch failures has been discussed in detail. The proposed topology uses phase disposition sinusoidal pulse width modulation (PD-SPWM) for gate signal generation. Further, a brief comparison analysis of the proposed topology in terms of device count, total blocking voltage (TBV), pre-and post-fault voltage level, pre-and post-fault voltage magnitude for the various fault combinations have been performed and compared with the exact nature of the available topology. The reliability analysis of the proposed topology has also been done mathematically. The simulation study of the proposed topology has been carried out in the MATLAB/SIMULINK environment for all possible switch fault combinations, and real-time validation is also done in OPAL-RT 4510. [ABSTRACT FROM AUTHOR] |
| Copyright of Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ) is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
|
Full text is not displayed to guests.
Login for full access.
|
|
| Abstract: | Due to the many semiconductor switches used in power conversion, switch failures are more common in multilevel inverters (MLIs). Therefore, designing an MLI with fault-tolerant (FT) capability is of utmost importance for uninterrupted supply. This article demonstrates various fault scenarios and offers numerous switching strategies for the different fault combinations. The detailed analysis of the proposed topology in terms of single (FT1), double (FT2), triple (FT3), quadruple (FT4), and quintuple (FT5) switch failures has been discussed in detail. The proposed topology uses phase disposition sinusoidal pulse width modulation (PD-SPWM) for gate signal generation. Further, a brief comparison analysis of the proposed topology in terms of device count, total blocking voltage (TBV), pre-and post-fault voltage level, pre-and post-fault voltage magnitude for the various fault combinations have been performed and compared with the exact nature of the available topology. The reliability analysis of the proposed topology has also been done mathematically. The simulation study of the proposed topology has been carried out in the MATLAB/SIMULINK environment for all possible switch fault combinations, and real-time validation is also done in OPAL-RT 4510. [ABSTRACT FROM AUTHOR] |
|---|---|
| ISSN: | 2193567X |
| DOI: | 10.1007/s13369-024-09713-z |
