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An energy-efficient adaptive two stage pipeline RISC-V based soft-processor for edge-computing applications.

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Title: An energy-efficient adaptive two stage pipeline RISC-V based soft-processor for edge-computing applications.
Authors: Kumar, Sujeet1 (AUTHOR) sujeet.kumar106@gmail.com, Ray, Kailash Chandra1 (AUTHOR)
Source: International Journal of Parallel, Emergent & Distributed Systems. Jan2026, Vol. 41 Issue 1, p89-103. 15p.
Subjects: Energy consumption, Edge computing, Reduced instruction set computers, Field programmable gate arrays, Adaptive control systems, Verilog (Computer hardware description language), Microprocessor design & construction
Abstract: This paper introduces a highly adaptable RV32I soft-processor architecture tailored for energy-restricted edge computing. Notably, it features a adptive two-stage pipeline with dynamic control to optimise energy consumption, activating the second stage selectively during memory operations. Implemented in Verilog HDL and validated on an FPGA platform, the architecture achieves impressive energy efficiency at 0.54 mW/M Hz. Comparative experiments demonstrate a substantial 28.2% reduction in average power usage compared to state-of-the-art single-cycle RV32I processors. These advancements position the design as highly suitable for energy-constrained edge computing applications, addressing critical efficiency challenges in resource-limited environments. [ABSTRACT FROM AUTHOR]
Copyright of International Journal of Parallel, Emergent & Distributed Systems is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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Header DbId: egs
DbLabel: Engineering Source
An: 190575066
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 0
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  Data: An energy-efficient adaptive two stage pipeline RISC-V based soft-processor for edge-computing applications.
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  Data: <searchLink fieldCode="AR" term="%22Kumar%2C+Sujeet%22">Kumar, Sujeet</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> sujeet.kumar106@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Ray%2C+Kailash+Chandra%22">Ray, Kailash Chandra</searchLink><relatesTo>1</relatesTo> (AUTHOR)
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  Data: <searchLink fieldCode="JN" term="%22International+Journal+of+Parallel%2C+Emergent+%26+Distributed+Systems%22">International Journal of Parallel, Emergent & Distributed Systems</searchLink>. Jan2026, Vol. 41 Issue 1, p89-103. 15p.
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  Data: <searchLink fieldCode="DE" term="%22Energy+consumption%22">Energy consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Edge+computing%22">Edge computing</searchLink><br /><searchLink fieldCode="DE" term="%22Reduced+instruction+set+computers%22">Reduced instruction set computers</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Adaptive+control+systems%22">Adaptive control systems</searchLink><br /><searchLink fieldCode="DE" term="%22Verilog+%28Computer+hardware+description+language%29%22">Verilog (Computer hardware description language)</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessor+design+%26+construction%22">Microprocessor design & construction</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: This paper introduces a highly adaptable RV32I soft-processor architecture tailored for energy-restricted edge computing. Notably, it features a adptive two-stage pipeline with dynamic control to optimise energy consumption, activating the second stage selectively during memory operations. Implemented in Verilog HDL and validated on an FPGA platform, the architecture achieves impressive energy efficiency at 0.54 mW/M Hz. Comparative experiments demonstrate a substantial 28.2% reduction in average power usage compared to state-of-the-art single-cycle RV32I processors. These advancements position the design as highly suitable for energy-constrained edge computing applications, addressing critical efficiency challenges in resource-limited environments. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of International Journal of Parallel, Emergent & Distributed Systems is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=190575066
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      – Type: doi
        Value: 10.1080/17445760.2024.2442001
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      – Code: eng
        Text: English
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        PageCount: 15
        StartPage: 89
    Subjects:
      – SubjectFull: Energy consumption
        Type: general
      – SubjectFull: Edge computing
        Type: general
      – SubjectFull: Reduced instruction set computers
        Type: general
      – SubjectFull: Field programmable gate arrays
        Type: general
      – SubjectFull: Adaptive control systems
        Type: general
      – SubjectFull: Verilog (Computer hardware description language)
        Type: general
      – SubjectFull: Microprocessor design & construction
        Type: general
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      – TitleFull: An energy-efficient adaptive two stage pipeline RISC-V based soft-processor for edge-computing applications.
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            NameFull: Kumar, Sujeet
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            NameFull: Ray, Kailash Chandra
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            – D: 01
              M: 01
              Text: Jan2026
              Type: published
              Y: 2026
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