View in EDS

Standard cell library based processor design using MGDI technique.

Saved in:
Bibliographic Details
Title: Standard cell library based processor design using MGDI technique.
Authors: S, Shankar1 (AUTHOR), S, Balamurali2 (AUTHOR), P, Sasipriya3 (AUTHOR), Angeline A, Anita3 (AUTHOR) anitaangeline.a@vit.ac.in
Source: International Journal of Electronics. Mar2026, Vol. 113 Issue 3, p465-478. 14p.
Subjects: Microprocessor design & construction, Reduced instruction set computers, Power measurement (Electricity), Multidisciplinary design optimization, Computer performance
Abstract: In the contemporary world, electronics play a massive role in every major application. There is always a demand for processors which have high performance in terms of power, delay and area. Various architectures are used in modern day applications but most of them are proprietary. However, they are quite restrictive, non-customisable and expensive. RISC-V being an instruction set architecture with open-source software and easily customisable makes it more reliable and facilitates in augmenting the architecture, instruction set and performance. In this paper, a 32-bit RISC-V processor is designed and implemented using the standard cells created using Modified Gate Diffusion Input (MGDI) technique through standard cell library characterisation. Standard cell characterisation is performed and ib and.lef files are generated using 180 nm library using Cadence Virtuoso tool. Semi-custom design of the 32-bit RISC-V processor and the synthesis using the customised standard cell library are done using the Cadence Genus tool and the analysis of power, delay and area are performed. In this paper, the comparison using minimum number of standard cells and increased number of standard cells in the library are analysed. [ABSTRACT FROM AUTHOR]
Copyright of International Journal of Electronics is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
Description
Abstract:In the contemporary world, electronics play a massive role in every major application. There is always a demand for processors which have high performance in terms of power, delay and area. Various architectures are used in modern day applications but most of them are proprietary. However, they are quite restrictive, non-customisable and expensive. RISC-V being an instruction set architecture with open-source software and easily customisable makes it more reliable and facilitates in augmenting the architecture, instruction set and performance. In this paper, a 32-bit RISC-V processor is designed and implemented using the standard cells created using Modified Gate Diffusion Input (MGDI) technique through standard cell library characterisation. Standard cell characterisation is performed and ib and.lef files are generated using 180 nm library using Cadence Virtuoso tool. Semi-custom design of the 32-bit RISC-V processor and the synthesis using the customised standard cell library are done using the Cadence Genus tool and the analysis of power, delay and area are performed. In this paper, the comparison using minimum number of standard cells and increased number of standard cells in the library are analysed. [ABSTRACT FROM AUTHOR]
ISSN:00207217
DOI:10.1080/00207217.2025.2518569