Analog/RF Performance Evaluation of Junctionless SOI FinFETs with Single, Double, and Triple Material Gates.
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| Title: | Analog/RF Performance Evaluation of Junctionless SOI FinFETs with Single, Double, and Triple Material Gates. |
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| Authors: | Edward, A. Shirly1 edwards@srmist.edu.in, Sharon, R. Linie2 lr4253@srmist.edu.in, Nagarajan, P.3 nagarajp@srmist.edu.in, Dey, Rajesh4 rajesh.dey@gnsu.ac.in, Oruganti, Sai Kiran5 saisharma@lincoln.edu.my |
| Source: | Engineering Letters. Jun2026, Vol. 34 Issue 6, p2437-2446. 10p. |
| Subjects: | Computer simulation, Signal integrity (Electronics) |
| Abstract: | This paper presents a comprehensive performance analysis of single, double, and triple material gate (SMGJL, DMGJL, TMGJL) Junctionless SOI FinFETs for Analog and RF applications using Technology Computer-Aided Design (TCAD) simulations at a 30 nm gate length. This study investigates key performance metrics, including Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), ON current (Ion), OFF current (Ioff), Ion/Ioff ratio, transconductance (gm), output conductance (gd), cut-off frequency (fT), and maximum oscillation frequency (fmax) for three different gate structures. The junctionless structure, along with SOI technology, enables simplified fabrication, improved electrostatic control, and reduced leakage currents. The simulation results indicate that the TMGJL FinFET exhibits superior performance, achieving the lowest SS (59.99mV/dec), highest Ion/Ioff ratio (6.11×10), and enhanced RF figures of merit (fT = 121.98GHz, fmax = 471.16GHz), making it highly suitable for next-generation low-power and high-frequency integrated circuits. Furthermore, the inverter circuit designed using the TMGJL FinFET exhibits high noise margin (NMH) of 0.500 V and low noise margin (NML) of 0.287 V, from the voltage transfer characteristics, indicating robust noise immunity of the simulated TMGJL FinFET. The comparative analysis demonstrates the advantages of multi-material gate engineering, with the TMGJL structure providing the best trade-off among switching behaviour, current drive capability, and RF/Analog performance. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
| Abstract: | This paper presents a comprehensive performance analysis of single, double, and triple material gate (SMGJL, DMGJL, TMGJL) Junctionless SOI FinFETs for Analog and RF applications using Technology Computer-Aided Design (TCAD) simulations at a 30 nm gate length. This study investigates key performance metrics, including Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), ON current (Ion), OFF current (Ioff), Ion/Ioff ratio, transconductance (gm), output conductance (gd), cut-off frequency (fT), and maximum oscillation frequency (fmax) for three different gate structures. The junctionless structure, along with SOI technology, enables simplified fabrication, improved electrostatic control, and reduced leakage currents. The simulation results indicate that the TMGJL FinFET exhibits superior performance, achieving the lowest SS (59.99mV/dec), highest Ion/Ioff ratio (6.11×10), and enhanced RF figures of merit (fT = 121.98GHz, fmax = 471.16GHz), making it highly suitable for next-generation low-power and high-frequency integrated circuits. Furthermore, the inverter circuit designed using the TMGJL FinFET exhibits high noise margin (NMH) of 0.500 V and low noise margin (NML) of 0.287 V, from the voltage transfer characteristics, indicating robust noise immunity of the simulated TMGJL FinFET. The comparative analysis demonstrates the advantages of multi-material gate engineering, with the TMGJL structure providing the best trade-off among switching behaviour, current drive capability, and RF/Analog performance. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 1816093X |
