View in EDS

Low-Power Ternary ALU with Reversible Gates and Gate Diffusion Multiplexers in the Carbon Nanotube Technology.

Saved in:
Bibliographic Details
Title: Low-Power Ternary ALU with Reversible Gates and Gate Diffusion Multiplexers in the Carbon Nanotube Technology.
Authors: Murali Krishna, P.1 (AUTHOR) murali.43@gmail.com, Vishnu Vardhan, D.1 (AUTHOR) vishnu.ece@jntu.ac.in
Source: IETE Journal of Research. Feb/Mar2026, Vol. 72 Issue 2/3, p586-595. 10p.
Subjects: Reversible computing, Power aware computing, Computer performance, Carbon nanotubes, Speed
Abstract: A Ternary Arithmetic Logical Unit (TALU) combines the adder, subtractor, and Ex-OR into a single module. Therefore, a novel design is proposed in this manuscript for TALU using multiple controlled reversible gates and the Gate Diffusion Input (GDI) technique-based multiplexer (TALU-GDI-MUX). The proposed ternary arithmetic logic unit (ALU) architecture includes a function selector, transmission gates (TG), and a rewritten functional module for abstraction. The functional module chooses the arithmetical or logical operations. The functional modules are designed using multiple controlled reversible gates with a GDI technique-based multiplexer, which provides the output of TALU operation, such as TALU1 and TALU0. This reduces transistor usage and power consumption while maximizing the speed. The TALU-GDI-MUX approach is implemented in HSPICE experimental tools. The TALU-GDI-MUX attains 23.53%, 15.64%, and 33.85% lower Delay, 32.43%, 14.84%, and 15.75% higher speed when compared to the existing techniques. [ABSTRACT FROM AUTHOR]
Copyright of IETE Journal of Research is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
Description
Abstract:A Ternary Arithmetic Logical Unit (TALU) combines the adder, subtractor, and Ex-OR into a single module. Therefore, a novel design is proposed in this manuscript for TALU using multiple controlled reversible gates and the Gate Diffusion Input (GDI) technique-based multiplexer (TALU-GDI-MUX). The proposed ternary arithmetic logic unit (ALU) architecture includes a function selector, transmission gates (TG), and a rewritten functional module for abstraction. The functional module chooses the arithmetical or logical operations. The functional modules are designed using multiple controlled reversible gates with a GDI technique-based multiplexer, which provides the output of TALU operation, such as TALU1 and TALU0. This reduces transistor usage and power consumption while maximizing the speed. The TALU-GDI-MUX approach is implemented in HSPICE experimental tools. The TALU-GDI-MUX attains 23.53%, 15.64%, and 33.85% lower Delay, 32.43%, 14.84%, and 15.75% higher speed when compared to the existing techniques. [ABSTRACT FROM AUTHOR]
ISSN:03772063
DOI:10.1080/03772063.2025.2568931