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Low-Power Ternary ALU with Reversible Gates and Gate Diffusion Multiplexers in the Carbon Nanotube Technology.

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Title: Low-Power Ternary ALU with Reversible Gates and Gate Diffusion Multiplexers in the Carbon Nanotube Technology.
Authors: Murali Krishna, P.1 (AUTHOR) murali.43@gmail.com, Vishnu Vardhan, D.1 (AUTHOR) vishnu.ece@jntu.ac.in
Source: IETE Journal of Research. Feb/Mar2026, Vol. 72 Issue 2/3, p586-595. 10p.
Subjects: Reversible computing, Power aware computing, Computer performance, Carbon nanotubes, Speed
Abstract: A Ternary Arithmetic Logical Unit (TALU) combines the adder, subtractor, and Ex-OR into a single module. Therefore, a novel design is proposed in this manuscript for TALU using multiple controlled reversible gates and the Gate Diffusion Input (GDI) technique-based multiplexer (TALU-GDI-MUX). The proposed ternary arithmetic logic unit (ALU) architecture includes a function selector, transmission gates (TG), and a rewritten functional module for abstraction. The functional module chooses the arithmetical or logical operations. The functional modules are designed using multiple controlled reversible gates with a GDI technique-based multiplexer, which provides the output of TALU operation, such as TALU1 and TALU0. This reduces transistor usage and power consumption while maximizing the speed. The TALU-GDI-MUX approach is implemented in HSPICE experimental tools. The TALU-GDI-MUX attains 23.53%, 15.64%, and 33.85% lower Delay, 32.43%, 14.84%, and 15.75% higher speed when compared to the existing techniques. [ABSTRACT FROM AUTHOR]
Copyright of IETE Journal of Research is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 194361301
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: Low-Power Ternary ALU with Reversible Gates and Gate Diffusion Multiplexers in the Carbon Nanotube Technology.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Murali+Krishna%2C+P%2E%22">Murali Krishna, P.</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> murali.43@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Vishnu+Vardhan%2C+D%2E%22">Vishnu Vardhan, D.</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> vishnu.ece@jntu.ac.in</i>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22IETE+Journal+of+Research%22">IETE Journal of Research</searchLink>. Feb/Mar2026, Vol. 72 Issue 2/3, p586-595. 10p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Reversible+computing%22">Reversible computing</searchLink><br /><searchLink fieldCode="DE" term="%22Power+aware+computing%22">Power aware computing</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+performance%22">Computer performance</searchLink><br /><searchLink fieldCode="DE" term="%22Carbon+nanotubes%22">Carbon nanotubes</searchLink><br /><searchLink fieldCode="DE" term="%22Speed%22">Speed</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: A Ternary Arithmetic Logical Unit (TALU) combines the adder, subtractor, and Ex-OR into a single module. Therefore, a novel design is proposed in this manuscript for TALU using multiple controlled reversible gates and the Gate Diffusion Input (GDI) technique-based multiplexer (TALU-GDI-MUX). The proposed ternary arithmetic logic unit (ALU) architecture includes a function selector, transmission gates (TG), and a rewritten functional module for abstraction. The functional module chooses the arithmetical or logical operations. The functional modules are designed using multiple controlled reversible gates with a GDI technique-based multiplexer, which provides the output of TALU operation, such as TALU1 and TALU0. This reduces transistor usage and power consumption while maximizing the speed. The TALU-GDI-MUX approach is implemented in HSPICE experimental tools. The TALU-GDI-MUX attains 23.53%, 15.64%, and 33.85% lower Delay, 32.43%, 14.84%, and 15.75% higher speed when compared to the existing techniques. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of IETE Journal of Research is the property of Taylor & Francis Ltd and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1080/03772063.2025.2568931
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 10
        StartPage: 586
    Subjects:
      – SubjectFull: Reversible computing
        Type: general
      – SubjectFull: Power aware computing
        Type: general
      – SubjectFull: Computer performance
        Type: general
      – SubjectFull: Carbon nanotubes
        Type: general
      – SubjectFull: Speed
        Type: general
    Titles:
      – TitleFull: Low-Power Ternary ALU with Reversible Gates and Gate Diffusion Multiplexers in the Carbon Nanotube Technology.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Murali Krishna, P.
      – PersonEntity:
          Name:
            NameFull: Vishnu Vardhan, D.
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 02
              Text: Feb/Mar2026
              Type: published
              Y: 2026
          Identifiers:
            – Type: issn-print
              Value: 03772063
          Numbering:
            – Type: volume
              Value: 72
            – Type: issue
              Value: 2/3
          Titles:
            – TitleFull: IETE Journal of Research
              Type: main
ResultId 1