View in EDS

Teaching the Cache Memory System Using a Reconfigurable Approach.

Saved in:
Bibliographic Details
Title: Teaching the Cache Memory System Using a Reconfigurable Approach.
Authors: Quislant, Ricardo1 quislant@ac.uma.es, Herruzo, Ezequiel2, Plata, Oscar1, Ignacio Benavides, José2, Zapata, Emilio L.1
Source: IEEE Transactions on Education. Aug2008, Vol. 51 Issue 3, p336-341. 6p. 7 Diagrams, 1 Chart.
Subjects: Cache memory, Instruction set architecture, Computer architecture, Computer systems, Electronic circuit design, Logic design
Abstract: This paper presents a tool that simulates a reconfigurable cache whose parameters can be changed at runtime through a special instruction at the instruction set architecture (ISA) level. The proposed tool simulates a cache system that can be reconfigured within a variety of 298 combinations of cache capacity, number of ways or associativity, and line/block size in words (C, W, and L) without changing its architecture. The simulator was developed through a series of laboratory exercises in computer architecture. The students are introduced to the reconfigurable cache architecture while refreshing their knowledge on computer architecture issues like logic design, and register transfer level and computer system level architectures, as well as reinforcing concepts about memory system organization and architecture. This paper presents an overview of the reconfigurable cache and a description of the simulator interface. Finally, feedback from the students provides assessment on using the simulator in the laboratory. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Education is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
Description
Abstract:This paper presents a tool that simulates a reconfigurable cache whose parameters can be changed at runtime through a special instruction at the instruction set architecture (ISA) level. The proposed tool simulates a cache system that can be reconfigured within a variety of 298 combinations of cache capacity, number of ways or associativity, and line/block size in words (C, W, and L) without changing its architecture. The simulator was developed through a series of laboratory exercises in computer architecture. The students are introduced to the reconfigurable cache architecture while refreshing their knowledge on computer architecture issues like logic design, and register transfer level and computer system level architectures, as well as reinforcing concepts about memory system organization and architecture. This paper presents an overview of the reconfigurable cache and a description of the simulator interface. Finally, feedback from the students provides assessment on using the simulator in the laboratory. [ABSTRACT FROM AUTHOR]
ISSN:00189359
DOI:10.1109/TE.2008.916767