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Synthesis and comparison of low-power high-throughput architectures for SAD calculation.

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Title: Synthesis and comparison of low-power high-throughput architectures for SAD calculation.
Authors: Walter, Fábio1, Diniz, Cláudio1 cmdiniz@inf.ufrgs.br, Bampi, Sergio1
Source: Analog Integrated Circuits & Signal Processing. Dec2012, Vol. 73 Issue 3, p873-884. 12p.
Subjects: Energy consumption, Electric distortion, Video coding, Energy dissipation, Household electronics
Abstract: Video applications are increasingly present in consumer electronic devices which require low-power and low-energy consumption. Sum of Absolute Differences (SAD) is the most used distortion metric in video coding implementation and consumes a relative large area in the motion estimation hardware. This paper presents the standard-cells synthesis and a comprehensive analysis of various parallel hardware architectures alternatives for SAD calculation, focusing on different design constraints such as high-performance (maximum throughput) and the tradeoff between high-performance and low-power dissipation (namely an isoperformance target). Low-power techniques supported by commercial standard-cells tools are exercised in this design, such as clock gating, multi-threshold (VT) and a combination of slow and fast standard-cells. We achieved significant power reduction for the architectures with lower frequencies and higher parallelism, slow cells and mainly with only one pipeline stage. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:Video applications are increasingly present in consumer electronic devices which require low-power and low-energy consumption. Sum of Absolute Differences (SAD) is the most used distortion metric in video coding implementation and consumes a relative large area in the motion estimation hardware. This paper presents the standard-cells synthesis and a comprehensive analysis of various parallel hardware architectures alternatives for SAD calculation, focusing on different design constraints such as high-performance (maximum throughput) and the tradeoff between high-performance and low-power dissipation (namely an isoperformance target). Low-power techniques supported by commercial standard-cells tools are exercised in this design, such as clock gating, multi-threshold (VT) and a combination of slow and fast standard-cells. We achieved significant power reduction for the architectures with lower frequencies and higher parallelism, slow cells and mainly with only one pipeline stage. [ABSTRACT FROM AUTHOR]
ISSN:09251030
DOI:10.1007/s10470-012-9971-z