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Centip3De: A 64-Core, 3D Stacked Near-Threshold System.

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Title: Centip3De: A 64-Core, 3D Stacked Near-Threshold System.
Authors: Dreslinski, Ronald G.1, Fick, David1, Giridhar, Bharan1, Kim, Gyouho1, Seo, Sangwon1, Fojtik, Matthew1, Satpathy, Sudhir1, Lee, Yoonmyung1, Kim, Daeyeon1, Liu, Nurrachman1, Wieckowski, Michael1, Chen, Gregory1, Sylvester, Dennis1, Blaauw, David1, Mudge, Trevor1
Source: IEEE Micro. Mar2013, Vol. 33 Issue 2, p8-16. 9p.
Subjects: Microprocessors, Dynamic random access memory, Energy consumption, Integrated circuit interconnections, Bandwidths
Abstract: Centip3De uses the synergy between 3D integration and near-threshold computing to create a reconfigurable system that provides both energy-efficient operation and techniques to address single-thread performance bottlenecks. The original Centip3De design is a seven-layer 3D stacked design with 128 cores and 256 Mbytes of DRAM. Silicon results show a two-layer, 64-core system in 130-nm technology, which achieved an energy efficiency of 3,930 DMIPS/W. [ABSTRACT FROM PUBLISHER]
Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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PubType: Academic Journal
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  Data: Centip3De uses the synergy between 3D integration and near-threshold computing to create a reconfigurable system that provides both energy-efficient operation and techniques to address single-thread performance bottlenecks. The original Centip3De design is a seven-layer 3D stacked design with 128 cores and 256 Mbytes of DRAM. Silicon results show a two-layer, 64-core system in 130-nm technology, which achieved an energy efficiency of 3,930 DMIPS/W. [ABSTRACT FROM PUBLISHER]
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  Data: <i>Copyright of IEEE Micro is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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