View in EDS

A high step-up switched capacitor six-level inverter.

Saved in:
Bibliographic Details
Title: A high step-up switched capacitor six-level inverter.
Authors: Wei, Jincheng1 (AUTHOR), He, Hesen1 (AUTHOR), Qiu, Xiaochu2 (AUTHOR) xh_qiusir@mail.xhu.edu.cn, Dong, Zhelin1 (AUTHOR), Li, Xinrong3 (AUTHOR)
Source: Electrical Engineering. Mar2026, Vol. 108 Issue 3, p1-14. 14p.
Subject Terms: *Capacitor switching, *Power semiconductor switches, *Modulation theory
Abstract: A novel six-level inverter topology based on switched capacitors is proposed to address the issues of complex topologies, difficulty in controlling capacitor voltage balance, and low voltage gain in traditional multilevel inverters. The topology consists of a DC power source, four capacitors, and nine power switches, achieving a voltage boost of 2.5 times, compared with traditional inverters such as NPC, ANPC and FC topologies, the proposed inverter topology does not require an intermediate DC boost stage. It effectively reduces the overall voltage stress on the switches and automatically balances the capacitor voltages without the need for complex control circuits. A detailed analysis of the proposed inverter's topology, operating principles, and carrier modulation strategy is provided, along with the design of key circuit component parameters and a thorough examination of the power losses in the switches. Simulation and experimental results demonstrate that the proposed topology offers advantages such as a simple structure, automatic capacitor voltage balancing, and high voltage boost gain, confirming its feasibility and effectiveness. [ABSTRACT FROM AUTHOR]
Database: Energy & Power Source
Description
Abstract:A novel six-level inverter topology based on switched capacitors is proposed to address the issues of complex topologies, difficulty in controlling capacitor voltage balance, and low voltage gain in traditional multilevel inverters. The topology consists of a DC power source, four capacitors, and nine power switches, achieving a voltage boost of 2.5 times, compared with traditional inverters such as NPC, ANPC and FC topologies, the proposed inverter topology does not require an intermediate DC boost stage. It effectively reduces the overall voltage stress on the switches and automatically balances the capacitor voltages without the need for complex control circuits. A detailed analysis of the proposed inverter's topology, operating principles, and carrier modulation strategy is provided, along with the design of key circuit component parameters and a thorough examination of the power losses in the switches. Simulation and experimental results demonstrate that the proposed topology offers advantages such as a simple structure, automatic capacitor voltage balancing, and high voltage boost gain, confirming its feasibility and effectiveness. [ABSTRACT FROM AUTHOR]
ISSN:09487921
DOI:10.1007/s00202-025-03494-w